COMPE 470
Digital Circuits

Catalog Description: Design of digital electronic systems using commercially available high-speed digital devices and circuits.

Credits: 3.0

Class Schedule: 2 lectures per week; 1 hour 15 minutes per session.

Prerequisites by topic: Fundamentals on modeling and analysis of digital systems primarily at the logic gate level; combinational and sequential networks.

Prerequisite by course: CompE270

Course Objectives:

  1. To learn all phases of digital system development, including design flow from initial specification to testable synthesized circuits in programmable logic
  2. To obtain engineering knowledge on the theory and practices involved in the CAD based design of digital systems
  3. To learn how to model a digital design using hardware descriptive language (HDL) such as VHDL
  4. To learn how to design and model both combinatorial and synchronous sequential logic circuits including finite state machines(FSM), arithmetic logic, data/control path using VHDL
  5. To learn a computer aided design tool (such as Xilinx Inc. ISE) to model digital design using VHDL for simulation, synthesis and timing analysis of digital systems targeting a programmable logic device such as a PLD/FPGA
  6. To learn and understand how to design test harnesses to simulate/analyze the digital design at both behavioral model level and post-synthesized model level using an industry standard simulation verification tool such as Modelsim

Textbooks and References:

  1. Kenneth L. Short, VHDL for Engineers, Prentice Hall, 2009.
  2. P. J. Ashenden, The Designer's Guide to VHDL, 2nd Ed., Morgan Kaufmann, 2001.
  3. S. Yalamanchili, Introductory VHDL from Simulation to Synthesis, Prentice-Hall, 2001.
  4. Roth, Fundamentals of Logic Design, 5th edition, Thomson, 2004.
  5. J. F. Wakerly; Digital Design: Principles and Practices 3rd Ed. Prentice Hall, 2001.

Topics Covered:

  1. Introduction to VHDL and Programmable Logic Devices (PLD)
    • History of VHDL
    • Design flow for the VHDL/PLD design methodology
    • What is VHDL design description?
    • How to verify a digital design using simulation?
    • Use of testbenches for generating input stimulus vectors
    • What is Functional/Behavioral simulation?
    • Introduction to Programmable logic devices (PLD; FPGAs)
    • What is logic synthesis?
    • Place-and-Route (P&R) and timing simulation/analysis
  2. VHDL modeling constructs
    • Design units, library units and design entities
    • Entity declaration syntax and port modes/definitions
    • Architecture body syntax and coding styles
    • Synthesis logic outcome versus coding style
    • Levels of abstraction and synthesis
    • Design hierarchy and structural design
    • Defining signals and data types
    • Logical Operations in VHDL
    • Boolean and relational operations
  3. Dataflow model for combinational Design
    • Signal assignments in dataflow models
    • Conditional signal assignments: select signal and conditional signal assignment
    • Modeling decoders, priority encoders in VHDL
    • Don’t care inputs/Outputs modeled in VHDL
    • Modeling lookup tables, three-state buffers
    • Avoiding loops in combinational logic model
  4. Behavioral model for combinational design
    • Writing Architecture using behavioral model
    • Process construct in VHDL and its uses
    • Defining/modeling sequential statements in VHDL
    • Case statements and its interpretation in VHDL
    • Conditional statements in processes: If statement
    • Loops in VHDL and its intended use
    • Variables in VHDL and its use
    • Difference between signals and variables
    • Synthesis of process that models combinational logic
  5. Behavioral model for sequential design
    • Defining memory in VHDL
    • Detecting clock edges and non-clock signal edges
    • Defining Latches and flipflops in VHDL
    • Timing requirements for synchronous input data
    • Modeling multibit latches, and registers in VHDL
    • Modeling shift registers, counters, modulo counters, and LFSRs in VHDL
    • Modeling synchronous and asynchronous memory in VHDL
  6. Testbenches for Combinational and sequential design
    • Event driven simulation
    • Delta delays in simulation
    • Design verification using testbenches
    • Functional verification of combinational logic
    • Writing testbenches in VHDL
    • Use processes to write testbenches that are event driven
    • Use of wait statements in writing testbenches and its use in simulation
    • Post-synthesis and timing verification for combinational design
  7. Modeling Finite State Machines (FSM)
    • What are FSMs?
    • Difference between a mealy and a moore FSM
    • Modeling a simple two-state FSM with three-process template using VHDL
    • Defining enumerated data types to encode states for a FSM
    • Modeling FSM in VHDL from a state diagram
    • FSM state encoding and state assignment
    • Writing safe FSM: Modeling defaults states to ensure FSM has a default state
    • Writing complex FSM for UART

Prepared by: Dr.Premanand Chandramani
Date of Preparation: 02/18/2009