COMPE 470L
Digital Logic Laboratory
Catalog Description:
Hands-on experience in characterization and application of standard digital integrated circuit devices.
Credits: 1.0
Class Schedule: One lab session per week, 2 hour 40 minutes per session
Prerequisites by topic: Fundamentals on modeling and analysis of digital systems primarily at the logic gate level; combinational and sequential networks.
Prerequisites by course: EE330L , and CompE470
Course Objectives:
- Know good lab practices and safety rules.
- Understand basic Digital Logic design and debugging techniques.
- Understand the operation and usage of measurement instruments (DMM, power supplies, signal generator, and oscilloscopes).
- Know basic laboratory measurement techniques and ground connections.
- Model a digital design using hardware descriptive language (HDL) such as VHDL
- Design and model both combinatorial and synchronous sequential logic circuits including finite state machines(FSM), arithmetic logic, data/control path using VHDL
- Use a computer aided design tool (such as Xilinx Inc. ISE) to model digital design using VHDL for simulation, synthesis and timing analysis of digital systems targeting a programmable logic device such as a PLD/FPGA
- Design test harnesses to simulate/analyze the digital design at both behavioral model level and post-synthesized model level using an industry standard simulation verification tool such as Modelsim
- Download/reconfigure the FPGA with the bit file generated after synthesis and verified
- Learn to record experimental data and write laboratory reports.
Textbooks and References:
- Kenneth L. Short, VHDL for Engineers, Prentice Hall, 2009.
- P. J. Ashenden, The Designer's Guide to VHDL, 2nd Ed., Morgan Kaufmann, 2001.
- S. Yalamanchili, Introductory VHDL from Simulation to Synthesis, Prentice-Hall, 2001.
- Roth, Fundamentals of Logic Design, 5th edition, Thomson, 2004.
- J. F. Wakerly; Digital Design: Principles and Practices 3rd Ed. Prentice Hall, 2001.
Topics Covered: Individual and Group Projects that are completed using CAD tools and logical implementation onto FPGA and addressing the following :
- Good lab practices and proper ground connections
- Experiment on “Seven Segment Display”
- Design 4-bit counters, Modes of operation: count up, count down and 4-digit code display
- Time multiplex the data to fours seven segment LED display using a shared data bus
- LED should display the counting sequence in hexadecimal or decimal format
- Display should be flicker free
- Experiment on “PS/2 Keyboard Driver”
- Display keyboard scan codes from ps/2 interface on the seven segment display
- Modes of operation: Most recent keycode or store and display any of the previous 4 keycodes
- Manual switch to choose between modes of operation
- Read all key presses from the ps/2 keyboard
- Display should be flicker free
- Experiment on “VGA Monitor Driver”
- Display at least 16 different color patters on the VGA monitor
- Design to display for a minimum monitor resolution of 640x480 pixels (VESA compliant)
- Monitor display pattern must never flicker and be stable until another pattern is activated
- Patterns must be representative of the available bit depths possible (3-bit, 8-bit, 24bits, etc.,)
- The display pattern selection my be driven on board or from the keyboard input
- Experiment on “UART Transmitter”
- Design and implement asynchronous serial transmitter which takes keyboard input and transmits that data as a serial readable signal
- ps/2 compliant keyboard interface
- Minimum baud rate of 115200 bps with optional parity and 1 or 2 stop bits
- Transmission shall adhere to RS232C standard using generic SCI
- Serial output shall be connected to PC serial terminal (miniterminal or Hyperterminal)
- Experiment on “Memory Chip Interface”
- Design and implement to store data from keyboard input on to an off-chip memory (SRAM)
- Clock synchronous Read and write data from the external memory
- Read data from memory and display it using the PC serial terminal (miniterminal or Hyperterminal)
Prepared by: Dr.Premanand Chandramani
Date of Preparation: 03/11/2009
