COMPE 475
Microprocessors

Catalog Description:

Bus design, memory design, interrupt structure, and input/output for microprocessor-based systems.

Credits: 3.0

Class Schedule: 2 lectures per week; 1 hour 15 minutes per session.

Prerequisites by topic: Fundamentals of computer organization and architecture, embedded processing, and digital logic design.

Prerequisite by course: CompE375 and CompE470

Course Objectives:

  1. Understand how to design the interface between a microprocessor and memory (RAM/ROM) and to input/output devices.
  2. Understand memory mapping and address decoding for all the peripherals that are interfacing with the microprocessor.
  3. Calculate and evaluate timing requirements for the microprocessor, memory and the input/output devices for system development and setup.
  4. Employ Xilinx ISE and EDK (Embedded Design Kit) to develop a Microblaze 32-bit softcore RISC processor based Hardware/software co-design. Use Xilinx ISE to develop custom data path logic. Enable interface from processor to its on-chip peripherals and memory through an IBM core-connect bus architecture.
  5. Design and develop projects that use Intellectual Property (IP) cores from Xilinx to interface with the Microprocessor to enable, Video interface (using I2C), RS232 interface for software debugging, Keyboard interface, LCD interface, SVGA interface and external memory interface.
  6. Implement the design projects on Xilinx University Program (XUP) supported “Curriculum on a Chip” prototype platform board that uses a Virtex II-pro FPGA from Xilinx that is embedded with PowerPC cores and several legacy based input/output interfaces.

Textbooks and References:

  1. Brey, Barry B., Embedded Controllers 80186, 80188, and 80386EX, Prentice-Hall, 1998. Mentor Graphics tutorials available on line and in the textbook Z. Navabi, VHDL: Analysis and Modeling of Digital Systems, 8th Ed., McGraw Hill, 2008.
  2. Z. Navabi, VHDL: Analysis and Modeling of Digital Systems, 2nd Ed., McGraw Hill, 1998.
  3. M. D. Cilette, Advanced Digital Design With Verilog HDL, Prentice-Hall 2002
  4. P. J. Ashenden, The Designer's Guide to VHDL, 2nd Ed., Morgan Kaufmann, 2001.
  5. C. H. Roth, Digital Systems Design Using VHDL, PWS, 1998.
  6. Pellerin and Taylor, VHDL Made Easy!, Prentice Hall, 1997.
  7. Brown and Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, 2000.
  8. J. F. Wakerly; Digital Design: Principles and Practices 3rd Ed. Prentice Hall, 2001

Topics Covered:

  1. Introduction to Programmable Logic Devices (PLD)
    • Design flow for the VHDL/PLD design methodology
    • Introduction to Programmable logic devices (PLD; FPGAs)
    • What is logic synthesis?
    • Place-and-Route (P&R) and timing simulation/analysis
    • How to verify a digital design using simulation?
    • Use of testbenches for generating input stimulus vectors
  2. Microprocessor and its Architecture
    • Internal Microprocessor Architecture and Multipurpose registers
    • Real Mode Memory addressing; Segment and Offset addressing
    • Protected Mode Memory Addressing; Selectors and Descriptors
    • Memory paging, paging registers and page table
  3. Intel 8088/8086 Hardware Specifications
    • Clock Generator Chip -8284A and its Operation
    • Bus Buffering and Latching, De-multiplexing buses
    • Bus timing: Bus Operation, Read Timing, Write timing
    • Ready and Wait States
    • Minimum and Maximum mode operation
    • 8288 Bus Controller – Maximum Mode Operation
  4. Memory Interface
    • Memory Devices: SRAM, ROM, DRAM
    • Address Decoding: 3-to-8 Line Decoder, 2-to-4 Line Decoder, PLD Programmable Decoders
    • 8088 and 80188 (8-bit) Memory Interface
    • 8086 and 80186 (16-bit) Memory Interface
  5. Basic I/O Interface
    • Isolated and Memory-Mapped I/O
    • Input/Output Port Addressing: 8-bit port address decoding and 16-bit port address decoding
    • Programmable Peripheral Devices (82C55) and its Modes of Operation
    • Programmable Interval timer (8254)
    • Programmable Communications Interface - UART (16550)
    • Modeling shift registers, counters, modulo counters, and LFSRs in VHDL
    • Modeling synchronous and asynchronous memory in VHDL
  6. Interrupts and Bus Interface
    • Basic Interrupt Processing
    • Hardware Interrupts
    • Programmable Interrupt Controller (8259A)
    • ISA Bus, PCI Bus
    • Parallel Port, Serial Port and USB Bus
  7. 80186 (16-bit) and 80188 (8-bit) Microprocessors
    • 80186/80188 Architechture
    • 80186/80188 timing
    • Programming 80186/80188 Peripherals
  8. Xilinx’s MicroBlaze 32-bit SoftCore RISC Processor
    • Architecture and General Purpose Registers
    • Bus Interfacing, MMU, and Interrupts
    • Configurable features of the Processor
  9. IBM Core Connect Bus Interface
    • Processor Local Bus (PLB)
    • On-Chip Peripheral Bus (OPB)
    • Local Memory Bus (LMB)
    • Device Control Register (DCR) Bus
    • Bus Arbitration and Bus Bridging
  10.  Project 1: Keyboard Interface and LCD Interface
    • Using XUP FPGA Prototype Board
    • KeyBoard Driver and Keyboard Interfacing
    • LCD Driver and LCD Interface
  11.  Project 2: Video Interfacing and Processing
    • VDEC Video Encoder Interface through I2C interface
    • Video Processing streaming Data: Line Buffering, Page buffering, Varying Resolution and Varying frame Rate
  12.  Project 3: Final Group Project
    • Individual Project that uses the varying features of the XUP board. Students choose the project with the approval of the course Instructor.
    • Hardware/Software based co-design using the softcore processor, IP cores and custom Cores.

Prepared by: Dr.Premanand Chandramani
Date of Preparation: 03/11/2009