COMPE 572
VLSI Circuit Design

Catalog Description:

Design of digital integrated circuits based on CMOS technology; characterization of field effect transistors, transistor level design and simulation of logic gates and subsystems; chip layout, design rules, introduction to processing; ALU architecture.

Credits: 3.0.

Class Schedule: 3 hours lecture per week.

Prerequisites: CompE271, EE 330

Course Objectives:  Upon completion of the course, students should be able to:

  1. Design standard logic gates, compound logic gates, and data path subsystems using transistor configurations.
  2. Design logic gates to meet timing specifications, and determine the power consumption in logic gates and subsystems.
  3. Generate the layout of a standard cell, check for design rule compliance, and place and route cells in a chip design.
  4. Calculate the current flow in CMOS transistors, the noise margin and logic threshold voltage of inverters, the propagation delay in logic gates, the dynamic and short circuit power consumption in logic gates and subsystems, and critical path delays.
  5. Analyze performance implications of changes in parameters like supply voltage, threshold voltage, and wiring widths.
  6. Write reports summarizing and interpreting the results of experiments using CAD (computer aided design) tools for layout and transistor level analog simulation.

Textbooks and References:

  1. CMOS VLSI Design (3rd ed.), N.H.E. Weste and D. Harris, Pearson, 2005.
  2. Digital Integrated Circuits(2nd ed.), J.M.Rabaey, et. al., Pearson, 2003

Topics Covered:    The following topics are covered in the course:   

  1. The switching model of n-channel and p-channel transistors and the implementation of standard restoring logic, compound, and transmission gates.
  2. The nature of the current-voltage characteristics of CMOS transistors and the development of equivalent circuit parameters.
  3. Derivation and interpretation of the low frequency voltage transfer characteristics of inverter configurations.
  4. The nature and behavior of tri-state and pseudo-nmos logic gates.
  5. The nature of certain basic physical properties of semiconductors like threshold voltage, channel mobility, and channel inversion and their impact on transistor behavior.
  6. Inverter latch-up and noise margin.
  7. The nature of chip manufacturing processes including layout and standard cell design .
  8. Circuit level modeling of logic gates, the sources of propagation delay, and the design of circuits to meet timing constraints.
  9. The design of buffers and the nature of the dynamic and short circuit power consumption in logic gates.
  10. The origin of noise spikes in VLSI circuits and the design of power and ground lines to meet current density specifications.
  11. Estimation of set-up and hold time for registers.
  12. Design dynamic logic gates including domino and zipper logic.
  13. The nature of timing constraints in finite state machines, and the design of clock signal generation and distribution circuits.
  14. Design of SRAM and content addressable memory structures at the transistor level.
  15. The transistor level design of processor data path components.
  16. The use of CAD (computer aided design) tools to generate the layout of standard cells and simulate the transistor level behavior of subsystems.

Prepared by:   Dr. Jay H. Harris
Date of Preparation:   02/10/2009